Memory cells, and in particular, non-volatile memory cells are widely used in countless electronics devices. Non-volatile memory cells utilize floating gate transistors, which are transistors that include a channel, source/drain regions, and both a control gate and a floating gate. The floating gate is disposed in a dielectric material between the control gate and the subjacent channel formed in a substrate.
In the manufacture of non-volatile memory cells and all semiconductor devices, there is a continued drive to increase levels of integration, a corollary of which is to reduce device feature size and increase the concentration of functional devices within a given area. It is challenging to manufacture a large number of floating gate transistors in close proximity because of their complexity. Limitations in photolithography and etching processes restrict the levels of integration, i.e., the reduction in device feature size and spacing, obtainable using lithography and etch processes. The lithography and etch processes typically used to form floating gate transistors on semiconductor substrates often produce stringers that undesirably short the floating gates together.
It is also a challenge to effectively increase the area of the floating gate so as to desirably enlarge the GCR, gate coupling ratio, of the transistors. A large GCR is typically associated with a larger floating gate electrode, which unfortunately requires more space and decreases levels of integration.
It would be desirable to produce non-volatile memory cells and floating gate transistors at high levels of integration and with high gate coupling ratios, without experiencing the aforementioned shortcomings.